Field of the Invention
The present invention relates to a wafer processing method for processing a semiconductor wafer having metal patterns formed on part of division lines at given intervals.
Description of the Related Art
In a semiconductor device fabrication process, a plurality of electronic circuits such as integrated circuits (ICs) and large-scale integrations (LSIs) are formed on the front side of a substantially disk-shaped workpiece such as a semiconductor wafer. The back side of the workpiece thus having the plural electronic circuits is ground to reduce the thickness of the workpiece to a predetermined thickness. Thereafter, a device area of the workpiece where the electronic circuits are formed is cut along division lines called streets by using a cutting blade to thereby divide the workpiece into a plurality of device chips. A cut groove formed along each division line on the front side of the workpiece is periodically imaged by using imaging means, and a deviation between a reference line set in the imaging means and the cut groove or a preset cutting position on the workpiece is measured. Then, the cutting position is corrected according to this deviation (see Japanese Patent Laid-Open No. 2012-151225, for example).